Implantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable medical device system, including a Deep Brain Stimulation (DBS) system.
As shown in FIGS. 1A-1C, an SCS system typically includes an Implantable Pulse Generator (IPG) 10 (Implantable Medical Device (IMD) 10 more generally), which includes a biocompatible device case 12 formed of a conductive material such as titanium for example. The case 12 typically holds the circuitry and power source (e.g., battery) 14 (FIG. 1C) necessary for the IPG 10 to function, although IPGs can also be powered via external RF energy and without a battery. The IPG 10 is coupled to electrodes 16 via one or more electrode leads 18, such that the electrodes 16 form an electrode array 20. The electrodes 16 are carried on a flexible body 22, which also houses the individual signal wires 24 coupled to each electrode. In the illustrated embodiment, there are eight electrodes (Ex) on two leads 18 for a total of sixteen electrodes 16, although the number of leads and electrodes is application specific and therefore can vary. The leads 18 couple to the IPG 10 using lead connectors 26, which are fixed in a non-conductive header material 28, which can comprise an epoxy for example.
As shown in the cross-section of FIG. 1C, the IPG 10 typically includes a printed circuit board (PCB) 30, along with various electronic components 32 mounted to the PCB 30, some of which are discussed subsequently. Two coils (more generally, antennas) are shown in the IPG 10: a telemetry coil 34 used to transmit/receive data to/from an external controller (not shown); and a charging coil 36 for charging or recharging the IPG's battery 14 using an external charger (not shown), although the IPG 10's battery may also be non-rechargeable, in which case the charging coil 36 would not be necessary. FIG. 1B shows these aspects in perspective with the case 12 removed for easier viewing. Telemetry coil 34 may alternatively comprise a short range RF antenna for wirelessly communicating in accordance with a short-range RF standard such as Bluetooth, WiFi, MICS, Zigbee, etc., as described in U.S. Patent Application Publication 2016/0051825.
FIG. 2A shows a prior art architecture 40 for the circuitry in IPG 10, which is disclosed in U.S. Patent Application Publications 2012/0095529, 2012/0092031 and 2012/0095519 (“ASIC Publications”), which are incorporated by reference in their entireties. Architecture 40 includes a microcontroller integrated circuit 50 and an Application Specific Integrated Circuit (ASIC) 60 in communication with each other by a bus 90. Stated simply, the microcontroller 50 provides master control for the architecture 40, while ASIC 60 takes commands from and provides data to the microcontroller. ASIC 60 provides specific IPG functionality. For example, and as explained in further detail below, ASIC 60 sends stimulation current to and reads measurements from the sixteen electrodes 16. ASIC 60 comprises a mixed mode IC carrying and processing both analog and digital signals, whereas microcontroller 50 comprises a digital IC carrying and processing only digital signals.
Microcontroller 50 and ASIC 60 comprise monolithic integrated circuits each formed on their own semiconductive substrates (“chips”), and each may be contained in its own package and mounted to the IPG 10's PCB 30. Architecture 40 may also include additional memory (not shown) for storage of programs or data beyond that provided internally in the microcontroller 50. Additional memory may be connected to the microcontroller 50 by a serial interface (SI) as shown, but could also communicate with the microcontroller 50 via bus 90. Bus 90 may comprise a parallel address/data bus, and may include a clock signal and various control signals to dictate reading and writing to various memory locations, as explained in the '529 Publication. Bus 90 and the signals it carries may also take different forms; for example, bus 90 may include separate address and data lines, may be serial in nature, etc.
As explained in the above-referenced ASIC Publications, architecture 40 is expandable to support use of a greater number of electrodes 16 in the IPG 10. For example, and as shown in dotted lines in FIG. 2A, architecture 40 may include another ASIC 60′ identical in construction to ASIC 60, thus expanding the number of electrodes supported by the IPG 10 from sixteen to thirty two. Various off-bus connections 54 (i.e., connections not comprising part of bus 90) can facilitate such expansion, and may further (e.g., by bond programming; see inputs M/S) designate ASIC 60 as a master and ASIC 60′ as a slave. Such differentiation between the ASICs 60 and 60′ can be useful, as certain redundant functionality in the slave ASIC 60′ can be disabled in favor of the master ASIC 60. Off-bus communications 54 can allow the voltage at the electrode nodes 61a (E1′-EN′) of one of the ASICs (60′; OUT1, OUT2) to be sent to the other ASIC (60; IN1, IN2) to be measured. Off-bus connections 54 are further useful in generation and distribution of a clock signal governing communications on the bus 90 as well as in the ASIC(s) 60. As these concepts are discussed in detail in the above-referenced ASIC Publications, they are not elaborated upon here.
FIG. 2B shows various functional circuit blocks within ASIC 60, which are briefly described. ASIC 60 includes an internal bus 92 which can couple to external bus 90 and which may duplicate bus 90's signals. Note that each of the functional blocks includes interface circuitry 88 enabling communication on the internal bus 92 and ultimately external bus 90, as the above-referenced ASIC Publications explain. Interface circuitry 88 includes circuitry to help each block recognize when bus 92 is communicating data with addresses belonging to that block. ASIC 60 contains several terminals 61 (e.g., pins, bond pads, solder bumps, etc.), such as those necessary to connect to the bus 90, the battery 14, the coils 34, 36, external memory (not shown). Terminals 61 include electrode node terminals 61a (E1′-EN′) which connect to the electrodes 16 (E1-EN) on the lead(s) 18 by way of DC-blocking capacitors 55. As is known, DC-blocking capacitors 55 are useful to ensure that DC current isn't inadvertently (e.g., in the event of failure of the ASIC 60's circuitry) injected into the patient's tissue, and hence provide safety to the IPG 10. Such DC-blocking capacitors 55 can be located on or in the IPG 10's PCB 30 (FIG. 1C) inside of the IPG's case 12. See U.S. Patent Application Publication 2015/0157861.
Each of the circuit blocks in ASIC 60 performs various functions in IPG 10. Telemetry block 64 couples to the IPG telemetry coil 34, and includes transceiver circuitry for wirelessly communicating with an external device according to a telemetry protocol. Such protocol may comprise Frequency Shift Keying (FSK), Amplitude Shift Keying (ASK), or various short-range RF standards such as those mentioned above. Charging/protection block 62 couples to the IPG charging coil 36, and contains circuitry for rectifying power wirelessly received from an external charger (not shown), and for charging the battery 14 in a controlled fashion.
Analog-to-Digital (A/D) block 66 digitizes various analog signals for interpretation by the IPG 10, such as the battery voltage Vbat or voltages appearing at the electrodes, and is coupled to an analog bus 67 containing such voltages. A/D block 66 may further receive signals from sample and hold block 68, which as the ASIC Publications explain can be used to measure such voltages, or differences between two voltages. For example, sample and hold circuitry 68 may receive voltages from two electrodes and provide a difference between them (see, e.g., VE1−VE2 in FIG. 3A, discussed subsequently), which difference in voltage may then be digitized at A/D block 66. Knowing the difference in voltage between two electrodes when they pass a constant current allows for a determination of the (tissue) resistance between them, which is useful for a variety of reasons.
Sample and hold block 68 may also be used to determine one or more voltage drops across the DAC circuitry 72 used to create the stimulation pulses (see, e.g., Vp and Vn in FIG. 3A, explained subsequently). This is useful to setting the compliance voltage V+ to be output by a compliance voltage generator block 76. Compliance voltage VH powers the DAC circuitry 72, and the measured voltage drops ensure that the compliance voltage VH produced is optimal for the stimulation current to be provided—i.e., VH is not too low as to be unable to produce the current required for the stimulation, nor too high so as to waste power in the IPG 10. Compliance voltage generator block 76 includes circuitry for boosting a power supply voltage such as the battery voltage, Vbat, to a proper level for VH. Such circuitry (some of which may be located off chip) can include an inductor-based boost converter or a capacitor-based charge pump, which are described in detail in U.S. Patent Application Publication 2010/0211132.
Clock generation block 74 can be used to generate a clock for the ASIC 60 and communication on the bus. Clock generation block 74 may receive an oscillating signal from an off-chip crystal oscillator 56, or may comprise other forms of clock circuitry located completely on chip, such as a ring oscillator. U.S. Patent Application Publication 2014/0266375 discloses another on-chip circuit that can be used to generate a clock signal on the ASIC 60.
Master/slave control block 86 can be used to inform the ASIC 60 whether it is to be used as a master ASIC or as a slave ASIC (e.g., 60′), which may be bond programmed at M/S terminal 61. For example, M/S terminal may be connected to a power supply voltage (e.g., Vbat) to inform ASIC 60 that it will operate as a master ASIC, or to ground to inform that it will operate as a slave, in which case certain function blocks will be disabled, as the ASIC Publications explain.
Interrupt controller block 80 receives various interrupts (e.g., INT1-INT4) from other circuit blocks, which because of their immediate importance are received independent of the bus 92 and its communication protocol. Interrupts may also be sent to the microcontroller 50 via the bus 90. Internal controller 82 in the ASIC 60 may receive indication of such interrupts, and act as a controller for all other circuit blocks, to the extent microcontroller 50 (FIG. 2A) does not handle such interrupt through the external bus 90. Further, each of the functional circuit blocks contain set-up and status registers (not shown) written to by the controller 82 upon initialization to configure and enable each block. Each functional block can then write pertinent data at its status registers, which can in turn be read by the controller 82 via internal bus 92 as necessary, or by the microcontroller 50 via external bus 90. The functional circuit blocks can function as simple state machines to manage their operation, which state machines are enabled and modified via each block's set-up and status registers.
Nonvolatile memory (NOVO) block 78 caches any relevant data in the system (such as log data). Additional memory (not shown) can also be provided off-chip via a serial interface block 84.
ASIC 60 further includes a stimulation circuit block 70, which includes circuitry for receiving and storing stimulation parameters from the microcontroller 50 via buses 90 and 92. Stimulation parameters define the shape and timing of stimulation pulses to be formed at the electrodes, and can include parameters such as which electrodes E1-EN will be active; whether those active electrodes are to act as anodes that source current to a patient's tissue, or cathodes that sink current from the tissue; and the amplitude (A), duration (d), and frequency (f) of the pulses. Amplitude may comprise a voltage or current amplitude. Such stimulation parameters may be stored in registers in the stimulation circuitry block 70. See, e.g., U.S. Patent Application Publications 2013/0289661; 2013/0184794.
Block 70 also includes a Digital-to-Analog Converter (DAC) 72 for receiving the stimulation parameters from the registers and for forming the prescribed pulses at the selected electrodes. FIG. 3A shows a simple example of DAC circuitry 72 as used to provide a current pulse between selected electrodes E1 and E2 and through a patient's tissue, R. DAC circuitry 72 as shown comprises two portions, denoted as PDAC 72p and NDAC 72n. These portions of DAC circuitry 72 are so named because of the polarity of the transistors used to build them and the polarity of the current they provide. Thus, PDAC 72p is formed from P-channel transistors and is used to source a current +I to the patient's tissue R via a selected electrode E1 operating as an anode. NDAC 72n is formed of N-channel transistors and is used to sink current −I from the patient's tissue via a selected electrode E2 operating as a cathode. It is important that current sourced to the tissue at any given time equal that sunk from the tissue to prevent charge from building in the tissue, although more than one anode electrode and more than one cathode electrode may be operable at a given time.
PDAC 72p and NDAC 72n receive digital control signals from the registers in the stimulation circuitry block 70, denoted <Pstim> and <Nstim> respectively, to generate the prescribed pulses with the prescribed timing. In the example shown, PDAC 72p and NDAC 72n comprise current sources, and in particular include current-mirrored transistors for mirroring (amplifying) a reference current Iref to produce pulses with an amplitude (A). PDAC 72p and NDAC 72n could however also comprise constant voltage sources. Control signals <Pstim> and <Nstim> also prescribe the timing of the pulses, including their duration (D) and frequency (f), as shown in the example waveform in FIG. 3B. The PDAC 72p and NDAC 72n along with the intervening tissue R complete a circuit between a power supply VH—the compliance voltage as already introduced—and ground. As noted earlier, the compliance voltage VH is adjustable to an optimal level at compliance voltage generator block 76 (FIG. 2B) to ensure that current pulses of a prescribed amplitude can be produced without unnecessarily wasting IPG power.
The DAC circuitry 72 (PDAC 72p and NDAC 72n) may be dedicated at each of the electrodes, and thus may be activated only when its associated electrode is to be selected as an anode or cathode. See, e.g., U.S. Pat. No. 6,181,969. Alternatively, one or more DACs (or one or more current sources within a DAC) may be distributed to a selected electrode by a switch matrix (not shown), in which case optional control signals <Psel> and <Nsel> would be used to control the switch matrix and establish the connection between the selected electrode and the PDAC 72p or NDAC 72n. See, e.g., U.S. Pat. No. 8,606,362. DAC circuitry 72 may also use a combination of these dedicated and distributed approaches. See, e.g., U.S. Pat. No. 8,620,436.
In the example waveform shown in FIG. 3B, the pulses provided at electrodes E1 and E2 are biphasic, meaning that each pulse includes a stimulation phase of a first polarity and an active recovery phase of an opposite polarity (along with additional phases that are not therapeutically meaningful that are described below). This is useful as a means of active recovery of charge that may build up on the DC-blocking capacitors 55. Thus, while charge will build up on the capacitors 55 during the stimulation phase, the active recovery phase will recover that charge, particularly if the total amount of charge is equal in each phase (i.e., if the area under the stimulation and active recovery pulse phases are equal). Recovery of excess charge on the DC-blocking capacitors 55 is important to ensure that the DAC circuit 72 will operate as intended: if the charge/voltage across the DC-blocking capacitors 55 is not zero at the end of each pulse, remaining charge/voltage will skew formation of subsequent pulses, which may therefore not provide the prescribed amplitude.
During the stimulation phase, electrode E1 acts as the anode or source for the current pulse, while electrode E2 acts of the cathode or sink for the current pulse. Thus, sourced current of the desired amplitude is issued from the PDAC 72p to E1 while sunk current of that same amplitude is drawn into the NDAC 72n from E2. This causes the current to flow from E1 to E2 through the patient's tissue (R). Notice that the pulses at E1 and E2 during the stimulation phase have the same amplitude (although of opposite polarities) and the same pulse width (pw), so that an excess of charge does not build up in the patient's tissue, R. The stimulation phase is eventually followed by the active recovery phase during which E1 acts as the cathode (sunk current is drawn into the NDAC 72n from E1) and E2 as the anode (source current is issued from PDAC 72p to E2), such that current flows through the tissue R in the opposite direction.
To ensure complete recovery of any stored charge, the active recovery phase is followed by a passive recovery phase. In this passive recovery phase, the decoupling capacitors C1-C2 connected to previously-active electrodes E1 and E2 are shorted to a common potential via passive recovery switches 96 (FIG. 3A). In the example illustrated, this common potential, Vbat, comprises the voltage of the battery within the IPG 100, although other reference potentials could be used as well. Shorting the capacitors to Vbat effectively shorts them through the patient's tissue, and thus equilibrates any stored charge to assist in charge recovery. Some architectures may short only the previously-active electrodes by closing only the passive recovery switches 86 coupled to those electrodes, while other architectures will short all of the electrodes by closing all of the passive recovery switches 96.
Other pulse phases in each period are shown in FIG. 3B. Preceding the stimulation phase is a pre-pulse phase, which is of low amplitude and long duration, and of opposite polarity to the stimulation phase that follows it. Experimentation suggests that the use of such a pre-pulse can help to assist in recruiting deeper nerves in an SCS application, although use of such a pre-pulse is not strictly necessary. An interpulse period between the stimulation and active recovery phases of short duration allows the nerves to stabilize after being stimulated. A quiet phase follows the passive recovery phase, and essentially acts as a waiting phase before the next period issues. The duration of the quiet phase will depend on the durations of the phases that precede it in the period, as well as the frequency (f) at which the pulse issues.
The various phases of each pulse are controlled by the stimulation circuitry 70, which provides digital control signals to the DAC circuitry 72. The stimulation circuitry 70 receives and stores the data necessary to define the various phases in each pulse. Such information is provided to the stimulation circuitry 70 from microcontroller 50 via buses 90 and 92. The microcontroller 50 in turn typically receives information about the structure of the pulses wirelessly from an external device, such as an external controller through which the patient or clinician could select the various pulse parameters (amplitude, pulse width, frequency), the electrodes, and whether they are to act as anodes or cathodes.
As illustrated in FIG. 3C, the stimulation circuitry includes a timer 94 and a register bank 98. The timer 94 stores the durations (pulse widths) of the phases in the pulse, while the register bank 98 stores control, amplitude, active electrode, and electrode polarity information for the phases. Thus, a first register in the timer 94 stores the pulse width of the first pulse phase in the period, the pre-pulse (pwpp) in the example of FIG. 3B, and the corresponding first register in the register bank 98 stores its amplitude (amppp), active electrode, and electrode polarities. A second register in the timer 94 stores the pulse width of the next pulse phase, the stimulation phase (pws), and the corresponding second register in the register bank 98 stores the amplitude (amps), active electrode, and electrode polarity for the stimulation phase. Data for subsequent pulse phases (interphase (ip), active recovery (ar), passive recovery (pr), and quiet (q)) are similarly stored in the timer 94 and register bank 98. The timer 94 may comprise a state machine in one example.
The control data in the registers (cntl) contains information necessary for proper control of the DAC circuitry 72 for each phase. For example, during the passive recovery phase, the control data (cntlpr) would instruct certain passive recovery switches 96 to close, and would disable the PDAC 72p and the NDAC 72n. By contrast, during active phases, the control data would instruct the passive recovery switches 96 to open, and would enable the PDAC 72p and the NDAC 72n. 
Each register in the register bank 98 is, in one example, 96 bits in length, with the control data for the phase in the first 16 bits, the amplitude of the phase specified in the next 16 bits, followed by eight bits for each electrode. Each of the eight electrode bits in turn specifies the polarity (P) of the electrode in a single bit, with the remaining 7 bits specifying the percentage (%) of the amplitude that that electrode will receive. Thus, for the pre-pulse phase, the polarity bit P for E1 would be a ‘1’, specifying that that electrode is to act as a cathode, and thus will sink current of the specified amplitude (amppp) to NDAC 72n. The remaining seven bits for E1 would digitally represent 100%, indicating that E1 is to receive the entirety of the cathodic current during the pre-pulse phase. In more complicated examples, the sourced or sunk currents could be shared between electrodes, and thus smaller percentages would be indicated in the trailing seven bits. The polarity bit P for E2 during the pre-pulse phase would be a ‘0’, specifying that that electrode is to act as an anode, and thus will receive current as controlled by PDAC 72p. Again, the remaining seven bits for E2 would digitally represent 100%, indicating that E2 is to receive the entirety of the anodic current during the pre-pulse phase.
The other registers in register bank 98 are programmed similarly for each phase. For example, all of the bits for E3-E8 in all of the registers would be set to zero for the example pulses of FIG. 3B, because those electrodes are not implicated. The amplitudes for the interphase (ampip), passive recovery (amppr), and quiet (amps) phases would be set to zero as those phases do not require the PDAC 72p or NDAC 72n to actively issue any current.
The goal of the stimulation circuitry 70 is to send data from an appropriate register in the register bank 98 to the DAC circuitry 72 at an appropriate point in time, and this occurs by control of the timer 94. As noted earlier, the pulse widths of the various phases are stored in the timer 94. Also stored at the timer is the frequency, f, of the pulse, the inverse of which (1/f) comprises the duration of each period. Knowing this period, the timer 94 can cycle through the durations of each of the pulse widths, and send the data in the register bank 98 to the DAC circuitry 72 at the appropriate time. Thus, at the start of the period, the timer 94 enables the multiplexer 99 to pass the values stored in the first register for the pre-pulse data to the DAC circuitry 72 to establish the pre-pulse phase at electrodes E1 and E2. After time pwpp has passed, the timer 94 enables the multiplexer 99 to pass the values stored in the second register for the stimulation phase to the DAC circuitry 72 to establish the stimulation phase at the electrodes E1 and E2. The other registers are similarly controlled by the timer 94 to send their data at appropriate times. This process of cycling through the various pulse phases continues, and eventually at the end of quiet phase, i.e., at the end of pwq, the timer 94 once again enables the pre-pulse data, and a new period of the pulse is established.
This approach for controlling the DAC circuitry 72 in accordance with each phase of the pulse period is adequate, but the inventors have found that this approach also suffers from certain shortcomings. A significant shortcoming is the lack of flexibility that the stimulation circuitry 70 provides to define more complex pulses. Because the parameters of each phase of a pulse are specified by dedicated registers in the register bank 98, pulses are limited to the number of phases that the register bank 98 is designed to accommodate (e.g., the six phases shown in FIGS. 3B and 3C) each of which specify a constant pulse amplitude. Therefore, more complex pulses having, for example, ramped portions cannot be created using the circuitry 70. The circuitry 70 could be modified to accommodate additional pulse phases to approximate ramped pulse portions using a stair-step approach, but this would require additional registers in the register bank 98. Assume, for example, that to form a suitably-smooth ramp it would be necessary to parse both of the stimulation and active recovery phases into ten smaller phases. The pulse would then comprise 24 different phases: the 20 phases needed in each of the stimulation and active recovery phases, the pre-pulse phase, the inter-pulse phase, the passive recovery phase, and the quiet phase. Because the register bank 98 must contain a register for each phase in the period, that bank 98 would then need 24 different registers. The 96 bits needed for each register in the bank 98 typically comprise flip flops, and so in this example 2304 (96*24) flip flops would be required, or more if the IPG 100 supports further numbers of electrodes.
Flip flops require significant layout area on the ASIC 60. Further, the flip flops consume power when they are clocked, which can lead to complexity in gating the clocks to save power. The problem of excessive layout space is compounded by the fact that the stimulation circuitry 70 may include multiple timer 94/register bank 98/multiplexer 99 units operating in parallel (although only a single example is shown). Based on the existing architecture, the ASIC 60 must either include an undue number of area-intensive registers in register bank 98 to potentially handle the design of complex pulses, or provide a limited number of such registers and forego the use of such complex pulses; neither option is desirable.
A better solution is therefore needed to address the aforementioned problems, and is provided by this disclosure.